1. Field of the Invention
The present invention relates to a pillar-shaped semiconductor device and a method for producing the pillar-shaped semiconductor device.
2. Description of the Related Art
In recent years, an SGT (Surrounding Gate MOS Transistor), a representative pillar-shaped semiconductor device, has been attracting attention as a semiconductor element providing a semiconductor device having a high integration degree. There has been a demand for a further increase in the integration degrees of semiconductor devices including SGTs.
In a standard planar MOS transistor, the channel extends in a horizontal direction parallel to the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (for example, refer to Japanese Unexamined Patent Application Publication No. 2-188966 and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)). For this reason, SGTs allow an increase in the density of semiconductor devices, compared with planar MOS transistors.
FIG. 7 is a schematic structural view of an N channel SGT. A Si pillar 100 (hereafter, a silicon semiconductor pillar will be referred to as a “Si pillar”) of P or i (intrinsic) conductivity type has at its upper and lower positions N+ regions 101a and 101b (hereafter, a semiconductor region having a high concentration of donor impurity will be referred to as an “N+ region”) in which one of the N+ regions serves as a source and the other one serves as a drain. The Si pillar 100 between the N+ regions 101a and 101b serving as the source and the drain serves as a channel region 102. A gate insulating layer 103 is formed so as to surround the channel region 102. A gate conductor layer 104 is formed so as to surround the gate insulating layer 103. In an SGT, the N+ regions 101a and 101b serving as the source and the drain, the channel region 102, the gate insulating layer 103, and the gate conductor layer 104 are formed within or on the single Si pillar 100. The area of an SGT in plan view corresponds to the area of a single source or drain N+ region in a planar MOS transistor. As a result, compared with circuit chips including planar MOS transistors, further reduction in the size of chips can be achieved in circuit chips including SGTs.
As illustrated in a schematic structural view in FIG. 8, for example, two SGTs 116a and 116b are formed at the upper and lower positions of a single Si pillar 115 to thereby achieve reduction in circuit area.
FIG. 8 is a schematic structural view of a CMOS inverter circuit in which an N channel SGT 116a is formed in a lower portion of the Si pillar 115, and a P channel SGT 116b is formed above this N channel SGT 116a. The Si pillar 115 is formed on an i-layer substrate 117 (hereafter, a semiconductor layer not containing a donor or acceptor impurity will be referred to as an “i-layer”) with an N+ region 121a therebetween. A SiO2 layer 118 is formed around the Si pillar 115 and on the i-layer substrate 117 and the N+ region 121a. In an intermediate portion of the Si pillar 115, an N+ region 121b is formed. In the Si pillar 115, a P+ region 122a (hereafter, a semiconductor region having a high concentration of an acceptor impurity will be referred to as a “P+ region”) is formed so as to be connected to the N+ region 121b. The top portion of the Si pillar 115 has a P+ region 122b. The N+ region 121a serves as a source of the N channel SGT 16a. The N+ region 121b serves as a drain of the N channel SGT 116a. The Si pillar 115 between the N+ regions 121a and 121b serves as a channel region 123a of the N channel SGT 116a. The P+ region 122b serves as a source of the P channel SGT 116b. The P+ region 122a serves as a drain of the P channel SGT 116b. The Si pillar 115 between the P+ regions 122a and 122b serves as a channel region 123b of the P channel SGT 116b. A gate insulating layer 119a of the N channel SGT 116a is formed so as to surround the channel region 123a. A gate conductor layer 120a of the N channel SGT 16a is formed so as to surround the gate insulating layer 119a. Similarly, a gate insulating layer 119b of the P channel SGT 116b is formed so as to surround the channel region 123b. A gate conductor layer 120b of the P channel SGT 116b is formed so as to surround the gate insulating layer 119b. In a surface layer portion of the N+ region 121a, a nickel silicide layer (NiSi layer) 125a is formed. A NiSi layer 125b is formed around both of the N+ region 121b and the P+ region 122a positioned at a central portion of the Si pillar 115. In an upper surface layer of the P+ region 122b in the top portion of the Si pillar 115, a NiSi layer 125c is formed. A ground wiring metal layer 126a is formed on the NiSi layer 125a. This ground wiring metal layer 126a is connected to a ground terminal VSS. An output wiring metal layer 126b is formed on the NiSi layer 125b. This output wiring metal layer 126b is connected to an output terminal Vo. A power supply wiring metal layer 126c is formed on the NiSi layer 125c. This power supply wiring metal layer 126c is connected to a power supply terminal VDD. Input wiring metal layers 127a and 127b are respectively formed on the gate conductor layers 120a and 120b. These input wiring metal layers 127a and 127b are connected to an input terminal Vi.
In FIG. 8, the NiSi layer 125b, which is connected to the N+ region 121b and the P+ region 122a in the central portion of the Si pillar 115, is formed by forming a nickel (Ni) film on the circumferential surfaces of the N+ region 121b and the P+ region 122a, subsequently carrying out heat treatment at about 450° C., for example, and removing the remaining Ni film on the circumferential surfaces. As a result, the NiSi layer 125b is formed from the circumference to the inside of the N+ region 121b and the P+ region 122a. In a case where the Si pillar 115 has a diameter of 20 nm, for example, the NiSi layer 125b is desirably formed so as to have a thickness of about 5 to about 10 nm in the horizontal direction parallel to the semiconductor substrate. NiSi has a linear expansion coefficient of 12×10−6/K. Si has a linear expansion coefficient of 2.4×10−6/K. The linear expansion coefficient of NiSi is about five times that of Si. Because of this large difference in linear expansion coefficient, during production, for example, during heat treatment, the NiSi layer 125b causes high strain due to stress within the Si pillar 115. This tends to result in defects such as bending and collapse of the Si pillar 115. The probability of occurrence of such defects further increases as the diameter of a Si pillar is decreased for the purpose of an increase in the integration degree of circuits, for example. The N+ region 121b and the P+ region 122a need to be formed within the Si pillar 115 with high accuracy with respect to the positions of the gate conductor layers 120a and 120b. In addition, while such problems are considered, the N+ region 121b and the P+ region 122a need to be connected to the output wiring metal layer 126b with certainty. In addition, since processing in the side surface of the Si pillar 115 is carried out, a method of connecting the gate conductor layers 120a and 120b to the input wiring metal layers 127a and 127b with certainty is necessary.